1. Technical Field
The present invention relates to a method and system for recovering digital data from a transmitted balanced signal; and, more particularly, to a receiver including an input circuit, a buffer circuit, and a calibration circuit.
2. Description of the Related Art
To reduce cost and improve performance, many new industry standards have been proposed in recent years which allow computer systems to communicate with each other at high data rates through serial links. For example, the ANSI (American National Standards Institute) Fibre Channel standard allows serial data communications up to 4 Gb/s. If copper cables are utilized when implementing a communication link, a signal output by a transmitter will be attenuated due to the cable resistance and phase-shifted due to the skin effect when received by a receiver at the opposite end of the cable. At the output of the transmitter, the eye diagram of the waveform will indicate that the amplitude of the signal is swinging from a maximum level to a minimum level with no phase jitter. For example, FIG. 1A depicts an eye diagram at the output of a transmitter. The maximum transmitted voltage level is illustrated at reference number 2. The minimum transmitted voltage level is depicted at reference number 4. FIG. 1B illustrates the eye diagram at a receiver input. Signal V.sub.IN is received. Due to attenuation and phase shifting, or jitter, the eyes have almost closed both vertically and horizontally. FIG. 1C depicts the eye diagram at the output of the receiver. A perfect receiver will restore the amplitude of the received signal to the maximum and minimum levels without adding any phase shift, or jitter. In addition, if the ANSI Fibre Channel standard rates are adhered to, the receiver must be able to operate at a very high speed.
The bandwidth and sensitivity of the receiver is determined primarily by the input stage circuit. When operating at lower speeds, a single differential amplifier is often used as the input stage, such as depicted in FIG. 2. FIG. 2 depicts a differential amplifier 6 connected to a buffer circuit 8. Differential amplifier 6 amplifies signal V.sub.IN. Buffer circuit 8 includes inverters 9 which invert and buffer the output of differential amplifier 6. However, when operating at higher speeds, the output of the differential amplifier does not swing from the maximum to the minimum levels described above.
An additional distortion occurs due to device mismatch. Transistors usually have a slightly different threshold voltage. This mismatch will cause two significant problems. First, in the input stage of the receiver, the offset voltage will be amplified by the differential amplifier and will be output with the signal. Second, in the buffer stage of the receiver, mismatch between the p-channel and n-channel transistors will cause a delay through the buffer which will result in a difference between the rising and falling edges of the signal. This contributes to a higher jitter at the output of the receiver.